Lead Engineer - CAD Physical Verification

Silicon Labs (NASDAQ: SLAB) is a global leader in low-power wireless connectivity, delivering embedded technology that connects devices and enhances everyday life. By integrating cutting-edge technology into highly advanced system-on-chips (SoCs), Silicon Labs empowers device makers with the solutions, support, and ecosystems necessary to develop sophisticated edge connectivity applications. Headquartered in Austin, Texas, the company operates in over 16 countries and serves as a trusted partner across smart home, industrial IoT, and smart city markets.

Key Responsibilities

- Provide support to design and layout teams by resolving physical verification (PV) related issues throughout the chip development cycle.
- Develop, maintain, and perform quality assurance on various physical verification rule decks including DRC, Dummy fill, Antenna, and other custom decks.
- Lead impact analysis meetings with stakeholders to discuss and implement updates to verification decks.
- Collaborate closely with cross-functional teams such as CAD, ESD, Design, Layout, Packaging, and foundry groups to gather requirements for deck development.
- Conduct code reviews and create custom QA test cases to ensure the accuracy and reliability of rule decks.
- Develop and automate PV flows and methodologies aimed at improving verification quality and optimizing performance.
- Evaluate and benchmark new tools and features to enhance verification processes.
- Work with external vendors to report, track, and resolve software bugs effectively.

Required Qualifications

- A minimum of 5 years of professional experience in a related role.
- Bachelor’s or Master’s degree in Electrical Engineering.
- Proficiency in developing and supporting DRC rule decks, including custom rules, using Calibre SVRF or similar languages.
- Experience in debugging PV issues in collaboration with design and layout engineers.
- Familiarity with physical verification tools such as PVS, Pegasus, Calibre RVE, Calibre DRV, and Virtuoso layout editor.
- Strong scripting skills in languages like PERL, Python, or Shell for developing custom automation scripts.
- Excellent communication skills, with experience in cross-team collaboration for gathering specifications, deck development, and leading impact analysis discussions.
- Ability to work independently with strong decision-making, attention to detail, and documentation capabilities.

Preferred Qualifications and Benefits

Experience in coding LVS, extraction, and PERC rule decks is considered a plus.

Joining Silicon Labs means becoming part of a highly skilled, close-knit team where each engineer contributes significantly to the product’s success. The company values work-life balance and fosters a welcoming, enjoyable work environment.

Benefits include:
- Equity rewards through Restricted Stock Units (RSUs)
- Employee Stock Purchase Plan (ESPP)
- Comprehensive insurance plans with outpatient coverage
- National Pension Scheme (NPS)
- Flexible work policies
- Childcare support

Silicon Labs is an equal opportunity employer committed to diversity and inclusion. Employment decisions are based solely on qualifications and job-related criteria, without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, disability, or any other protected characteristic under applicable law.