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概要
I am an Electrical Engineer graduated in 2015 from UET Taxila, with CGPA 3.37. I did MS in Electrical Engineering (Digital systems) from SEECS, NUST with CGPA of 3.20. I have expertise in embedded system.
My final year project was "Three phase digital firing angle control using PIC 18f452 micro-controller" I do programming for interfacing of LCD, ADC, RS-232,UART, interrupts, and timers of micro-controller and generate firing pulses for SCRs. This final year project was sponsored from NECOP. It was an application of embedded systems.
My MS thesis is "Formal Timing Analysis of Digital circuits". First a digital circuit is converted to a state diagram, then timings constraints are added to that state diagram and then this is implemented in model checker UPPAAL. Information about total paths present in a circuit is obtained using Quartus prime pro timing analyzer. Final model is verified through TCTL queries. It was related to verification of digital systems.
I also have one year experience as a Research Assistant in NUST (SEECS) and worked on project Automatic Formal verification of verilog models of combinational circuits. I did 2 month summer internship in NECOP, where I worked on FPGA spartan 3 and Atmel AVR micro-controller. I worked on project "Image dehazing on FPGA".
I have two International Publications.
项目
工作经历
Research Associate
Worked on research based project which is Fomal Verification of Verilog models of Combinational Circuit.
Internee
I did two month intership in NECOP. I worked on atmet AVR micro-controller and FPGA spartan 2 kit
Internee
I did 6 week summer internship in PTCL where I learned about distribution of electricity from transformer to whole PTCL headquarter building.
