UST is seeking a Senior SoC/FPGA Verification Engineer with strong expertise in C/C++ based pre-silicon verification, embedded processor validation, and UVM-based verification methodologies. The successful candidate will play a key role in driving the verification of complex FPGA and SoC platforms, working closely with architecture, RTL, firmware, and validation teams to ensure robust system functionality and first-pass silicon success. This role demands deep knowledge of software-driven verification, embedded processor validation, and verification framework development.
Key Responsibilities:
- Develop and execute comprehensive verification strategies for FPGA and SoC designs.
- Create C/C++ based test cases and verification frameworks for embedded processor and subsystem validation.
- Develop and enhance SystemVerilog/UVM testbenches for IP, subsystem, and SoC-level verification.
- Verify CPU, memory, DMA, interrupt, boot, and peripheral subsystems across multiple use cases.
- Drive coverage-driven verification using constrained-random and directed testing methodologies.
- Develop assertions, checkers, scoreboards, and coverage models to improve verification quality.
- Debug complex functional issues across RTL, firmware, and system-level environments.
- Collaborate with architecture, design, firmware, and validation teams throughout the development cycle.
- Develop automation and productivity enhancements using Python, Shell, Perl, and Tcl scripting.
- Participate in design reviews, verification sign-offs, and methodology improvements.
Required Qualifications:
- Bachelor’s or Master’s degree in Electronics & Communication Engineering, Electrical Engineering, Computer Engineering, or related field.
- Minimum of 4 years’ experience in FPGA/ASIC functional verification.
- Strong expertise in C-based or embedded software-driven pre-silicon verification.
- Hands-on experience developing C/C++ test cases and verification frameworks for FPGA/SoC verification.
- Experience with RISC-V, ARM-based SoCs, or embedded CPU verification.
- Solid understanding of FPGA architectures and SoC subsystem design.
- Good knowledge of memory architectures, interrupts, DMA, boot flows, and embedded processors.
- Proficient in SystemVerilog and UVM verification methodologies.
- Strong understanding of constrained-random, directed, coverage-driven, and assertion-based verification techniques.
- Proficient scripting skills in Python, Shell, Perl, and Tcl.
- Excellent debugging, analytical, and problem-solving skills.
- Strong verbal and written communication skills.
Preferred Qualifications and Benefits:
- Experience in end-to-end SoC verification and subsystem integration.
- Knowledge of AMBA protocols such as AXI, AHB, and APB.
- Familiarity with simulation tools like VCS, Xcelium, or Questa.
- Experience with firmware-driven verification environments.
- Skilled in verification automation and regression infrastructure development.
- Exposure to FPGA prototyping and post-silicon validation is a plus.
- Experience leading verification efforts and mentoring junior engineers.
UST values humility, humanity, and integrity, fostering a culture of innovation, diversity, and inclusion. The company is committed to building enduring relationships and placing people at the center of everything it does. UST is an Equal Opportunity Employer, ensuring all employment decisions are made without regard to age, race, gender, disability, or any other protected status under applicable laws.
Candidates joining UST will be expected to support and promote the company’s core values, comply with all policies and procedures, and adapt roles and responsibilities as needed to meet organizational goals.
Keywords: ARM, C++, ASIC, Constrained Random Verification, Bootloaders, Embedded Systems, Hardware Architecture, Pre-Silicon Validation.
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