Co-Founder & CTO — AI Accelerator / ASIC Architecture

NeuraSilicon, an early-stage semiconductor startup, is developing the NS A400, an AI-native accelerator platform designed for next-generation AI compute, agentic workloads, and hardware/software co-design. The company is building a vertically integrated compute stack that includes NeuraCore, memory architecture, Neura ISA, NeuraCompiler, AI execution framework, RTL, FPGA validation, and ASIC development. We are seeking a highly skilled and motivated international technical co-founder to join as Co-Founder & CTO, focusing on AI accelerator and ASIC architecture. This is a hands-on founding role for someone passionate about designing a new AI compute architecture from the ground up, not just a title.

Key Responsibilities
- Take major technical ownership of NS A400 hardware development and architecture.
- Lead microarchitecture design for NS A400 and NeuraCore.
- Develop RTL using Verilog/SystemVerilog, including processing-element design, pipelines, control logic, and memory hierarchy.
- Design SRAM interfaces, DMA, cache architecture, interconnect/NoC, and perform RTL verification.
- Oversee FPGA prototyping, synthesis, and performance modeling.
- Drive hardware/software co-design, integrating Neura ISA hardware interfaces and NeuraCompiler.
- Define the ASIC architecture roadmap and lead future silicon engineering teams.
- Work directly on technical architecture rather than solely managing engineers.

Required Qualifications
- Strong experience or demonstrated ability in Verilog/SystemVerilog and RTL design.
- Proven skills in FPGA development and ASIC/VLSI design.
- Solid understanding of computer architecture, including GPU, NPU, or AI accelerator architecture.
- Expertise in digital logic, pipeline architecture, memory systems, SRAM/cache hierarchy, RTL verification, synthesis, timing concepts, and performance modeling.
- Demonstrated engineering ability with a track record of building complex systems.

Preferred Qualifications and Benefits
- Experience with RISC-V, AXI, NoC, PCIe, DMA, SIMD/vector architectures, tensor/matrix accelerators, CUDA/GPU architecture, LLVM/MLIR.
- Familiarity with tools such as Vivado, Quartus, Verilator, Yosys, OpenROAD, and RTL-to-GDSII flows.
- Background in semiconductor companies, CPU/GPU teams, AI accelerator startups, FPGA or ASIC engineering, RISC-V development, computer architecture research, university labs, or open-source silicon projects.
- Exceptional graduate students, researchers, independent engineers, and open-source contributors are encouraged to apply.

We value candidates who love building challenging systems, can write and review RTL, think deeply about compute and memory architecture, challenge technical assumptions, prototype quickly, understand performance bottlenecks, and seek long-term technical ownership. Candidates should be comfortable working across hardware and software domains and be motivated to build a semiconductor company from the ground up.

The NS A400 development is at an early stage, including memory simulation, balanced NeuraCore, Neura ISA, NeuraCompiler, AI execution framework, RTL, FPGA prototyping, and ASIC path. This offers a unique opportunity to influence fundamental design decisions. The near-term goal is to deliver an end-to-end NS A400 prototype demonstrating AI workloads, compiler integration, ISA, core, memory system, performance analysis, RTL, and FPGA validation. Key performance metrics will include compute utilization, memory bandwidth, latency, throughput, scaling, power/energy modeling, and hardware efficiency.

This is an early-stage co-founder role and is currently unpaid. It is not a conventional salaried CTO position. The selected candidate will receive meaningful founder equity with mutually agreed vesting terms. The intention is to transition to full-time compensated roles as financing permits. NeuraSilicon is preparing for the Y Combinator Winter 2027 application cycle.

This position is fully remote and open to exceptional candidates worldwide, with particular interest from regions including the United States, Canada, Europe, UAE, Singapore, Taiwan, South Korea, Japan, Australia, India, and other global semiconductor and AI engineering hubs.

Applicants should provide a portfolio or GitHub link, highlight their strongest RTL, FPGA, ASIC, CPU, GPU, or accelerator project, describe their strongest technical area, current location and time zone, availability, weekly commitment, willingness to transition to full-time upon funding, motivation for building an AI semiconductor startup, preferred NS A400 component to own, and one fundamental improvement they believe current GPU/AI accelerator architectures need.

NeuraSilicon is committed to building the next generation of AI compute—from architecture and compiler to silicon.