Design Verification Engineer

Snova Technologies, established in 2019, is a leading semiconductor engineering company specializing in high-speed connectivity solutions for AI, data centers, and high-performance computing silicon. The company’s expertise spans advanced interconnect technologies such as Ethernet, UALink, UEC, UCIe, PCIe, and chip-to-chip connectivity, alongside RISC-V and Edge AI compute platforms. Snova delivers digital design, custom IP development, integration, verification, and FPGA-based prototyping services to top semiconductor and system companies. Its engineering teams focus on AI accelerators, NICs, switches, chiplet-based SoCs, and AI infrastructure through project-based engagements, dedicated teams, and customized IP solutions.

Key Responsibilities
The Design Verification Engineer will be based on-site in Lahore, working full-time with design and architecture teams to verify complex digital IP and subsystems tailored for AI, data center, and HPC connectivity applications. Core duties include developing comprehensive verification plans, constructing and maintaining robust testbenches, writing and executing detailed test cases, and performing both functional and formal verification of RTL designs. The role requires analyzing design specifications, modeling expected behaviors, and identifying corner cases to ensure thorough validation. The engineer will utilize industry-standard verification methodologies and tools to guarantee silicon quality. Additional responsibilities include debugging failing tests, conducting root-cause analysis, documenting verification outcomes, and contributing to the continuous enhancement of verification flows and infrastructure.

Required Qualifications
Candidates must demonstrate strong functional verification expertise, including experience in testbench development, test planning, and coverage-driven verification techniques. Proficiency in formal verification methods and tools to validate complex digital logic and corner-case scenarios is essential. Hands-on experience with RTL design using Verilog or SystemVerilog is required, along with a solid understanding of synthesis, timing, and design constraints. A strong foundation in computer architecture—covering pipelines, memory hierarchies, interconnects, and protocol-level behavior—is necessary. Excellent debugging skills for both simulation and hardware environments are critical, with the ability to identify, reproduce, and resolve design and verification issues efficiently. Familiarity with industry-standard EDA tools and verification methodologies such as UVM, constrained-random stimulus, and coverage analysis is highly advantageous. Candidates should hold a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a closely related field. Effective collaboration skills, clear communication, and ownership of verification deliverables are also important.

Preferred Qualifications and Benefits
Experience with high-speed interfaces like Ethernet, PCIe, UCIe, or similar protocols, as well as background in AI or SoC design, will be considered a strong plus. The position offers the opportunity to work on cutting-edge semiconductor technologies within a dynamic and innovative environment, contributing to impactful projects in AI and high-performance computing sectors.