DFT Engineer (Entry / Mid / Senior)

We are looking for a skilled DFT Engineer to join our ASIC test team, responsible for the complete spectrum of Design-for-Test (DFT) activities. This role involves defining, implementing, and debugging DFT architectures through both pre-silicon and post-silicon phases. The successful candidate will collaborate across multiple teams to ensure high test coverage, cost-effective testing, and scalable DFT solutions tailored for complex System-on-Chip (SoC) and multidie designs.

Key Responsibilities

- Define and lead DFT architecture and methodologies at block, chip, and package levels.
- Insert, verify, and validate scan chains and compression techniques, including RTL and gate-level (SDF) simulations.
- Generate, validate, and analyze ATPG patterns (stuck-at and at-speed) to achieve coverage targets required for signoff.
- Design and implement test clocking architectures, including On-Chip Clock Controller (OCC) for multi-clock SoCs.
- Define and support memory test, repair, and configuration flows such as MBIST, BISR, and OTP/eFUSE programming and validation across pre- and post-silicon stages.
- Implement and optimize Boundary Scan (BSCAN) and Embedded Boundary Scan (EBSCAN) methodologies.
- Develop and support multidie DFT architectures (chiplet, 2.5D, 3DIC), including SSN and packetized test delivery.
- Support hierarchical DFT and ATPG retargeting, including tile-based architectures.
- Integrate DFT for third-party IPs using JTAG/IJTAG/IEEE1500 standards, ensuring compliance with vendor test guidelines.
- Collaborate on silicon bring-up, Automated Test Equipment (ATE) setup, pattern validation, and failure debug.
- Work closely with yield and product teams to enhance test coverage and reduce overall test costs.

Required Qualifications

- Bachelor’s or Master’s degree in Electrical or Computer Engineering.
- Hands-on experience with Mentor Tessent tools, including TestKompress, SSN, OCC, and IJTAG.
- Strong understanding of DFT fundamentals such as scan chains, compression, ATPG, fault simulation, MBIST, and LBIST.
- Experience with OCC, test clocking, and static timing analysis (STA) interactions in scan and at-speed testing modes.
- Knowledge of multidie and chiplet test architectures.
- Familiarity with Process Design Kits (PDK), synthesis, and physical design flows, and understanding of how DFT structures impact timing, clocking, and physical implementation.
- Proficiency in scripting languages such as TCL, Perl, Python, or Shell.
- Working knowledge of hardware description languages (Verilog/VHDL), simulation, waveform debugging, and Linux/Unix environments.
- Understanding of IEEE standards including JTAG/IEEE 1149, IJTAG/IEEE 1687, and IEEE1500.

Experience Level

- Entry Level: 0 to 3+ years of experience in DFT, ASIC, or SoC testing.
- Mid Level: 3 to 7+ years of hands-on DFT implementation experience.
- Senior Level: 7+ years of experience owning SoC-level DFT and test architectures.

This role offers the opportunity to work on cutting-edge SoC and multidie designs, contributing to robust and scalable test solutions in a collaborative environment. Candidates with a strong technical foundation and a passion for innovation in test engineering are encouraged to apply.