Principal Design Engineer
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6 Years
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First Shift (Day)
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Reliability
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Analog Circuit Design
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Jitter
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Problem-Solving
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Performance
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Power
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Communication
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Leadership
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PCIe Gen3/4/5/6
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Signal Integrity (SI)
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Power Integrity (PI)
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High-Speed Interface Design
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and Area (PPA) optimization
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UCIe
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Die-to-Die (D2D)
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DDR/LPDDR
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HBM
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GDDR
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SerDes architectures
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Analog Design fundamentals
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Principal Design Engineer

Cadence Design Systems, Hyderabad, Pakistan
Cadence is looking for a Principal Engineer with deep expertise in Analog Circuit Design to join our innovative team. This role focuses on d..
Sep 05, 2026 6 Years
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